EddyHawk's Info List
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INTEL
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8088
 16 bit
 word-alignment has no effect for data fetching
8086
80186
 bug: IDIV
80286
 more opcodes:
 -ENTER
 -LEAVE
 -PUSH immediate
 -extended IMUL, SHL, SHR
 protected mode (max 16Mb memory?)
 shift+add is faster than MUL
80386
 32 bit
 more opcodes: MOVSD
 protected mode (max 4Gb memory)
 bug:
 -32 bit multiply
 -POPAD
 -INSB
 -STOSB
 -MOVSB
 optimize: dec jnz is faster than loop
 PIQ (Prefetch Instruction Queue) ?
80486
 more opcodes: BSWAP
80586 (Pentium)
 bug: FDIV
 branch prediction
  under branch instruction, we can't determine which instruction 
   sequences should be prefetch-ed until the jmp is executed. If processor
   choose IQ before jmp & the IQ is proved to be wrong after jmp is
   executed, then the pipeline must be refilled, which is costly, especially
   on larger PIQ
  then the branch prediction is added to try to guess which IQ to be taken,
   based on previous jmps record (Branch Target Buffer)
Pentium Pro
 2 level branch prediction, much more powerful than previous branch
  prediction
 4-bit history
 16 x 2 bit pattern (total 32 bit)
 capable to
  learn repetitive branch pattern
  handle 16 different pattern
 MMX
  introduced at begin of 1997
  MMX register is mapped to FPU register
Celeron:
Pentium II:
Pentium III:
 MMX2 or SSE (Streaming SIMD (Single Instruction Multiple Data) Extension)
Pentium 4:
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AMD (Advanced Micro Device)
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K5
K6
 K6-2 (+3DNow!)
 K6-3
K7 (Athlon)
 Giga Athlon
 Thunderbird (copper interconnect)
 Mustang (optimized Thunderbird, for mobile computer)
 Spitfire (Duron, low cost Thunderbird?)
Sledgehammer (64bit)
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Cyrix
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6x80686
MediaGX
M II
 1st appearance: 1998
 >= 300mhz
 supports MMX
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NEC
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V20
V30
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UMC
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NEXGEN
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586
 uses 386 instruction set
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MOTOROLA
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68000